1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing and, more specifically, to the design of copper based interconnections in sub-micron dimensions with reduced sensitivity for corrosion and defects, and thereby, with improved reliability. The invention also relates to providing methods for forming the designed structure.
2. Description of Related Art
As device geometry continues to scale down for Ultra Large Scale Integrated circuits, there is a growing demand for an interconnect wiring with minimum pitch and high conductivity, and, for a passivation material with a low dielectric constant, while requiring a more robust reliability than ever before.
One approach has been to use copper metallurgy, for its high conductivity and high electromigration resistance, along with polyimide passivation for low cross capacitance. A process utilizing this approach is disclosed by Luther et al. in VLSI Multilevel Interconnection Conference (VMIC), pp.15-21, 1993. Further process improvement, using a double damascene method to simultaneously form copper interconnection lines and inter-level via-studs, is taught by Dalal et al. in U.S. Pat. No. 5,434,451, of common assignee with the present application. Damascene methods involve filling of narrow trenches or narrow holes or a combination of both. It is well known in the art that the use of Physical Vapor Deposition (PVD) methods such as sputtering or evaporation to fill such narrow holes and trenches is not suitable because a highly tapered cross section of the filled metal lines or studs is formed. Joshi with the present application, teaches using PVD methods to deposit the high conductivity metal followed by Chemical Vapor Deposition (CVD) of a tungsten cap layer to fill up the top part of the tapered cross section. This capping process results in substantial reduction in cross-sectional area of copper conductor because of the tapered cross-section. Also, because the capping metal is deposited along with the conductor metal, slits of conductor metal are exposed along the conductor edges in the finished product. Further, during the chemical-mechanical polishing. step in this capping process, the hard metal particles removed by polishing tend to abrade the metal line. Therefore, conformal deposition methods such as CVD or electroplating are required for copper deposition.
However, it has been found that CVD copper suffers from limited shelf life of the highly complex precursors required. A more serious problem with CVD copper is the contamination of manufacturing line by vapors of copper precursor, which poison the semiconductor devices.
Copper deposition by electroplating has been in use for Printed Circuit Board (PCB) for decades. Because of its low cost, low deposition temperature and its ability to conformally coat narrow openings, electroplating is a preferred method of deposition in copper interconnections. It should be understood that electroplating of copper requires a copper seed layer on the substrate. Invariably, a PVD method has been used to deposit copper for seed layer. However, it has been found that PVD deposited copper has ten times lower electromigration resistance, as compared to electroplated copper; and three times lower electromigration resistance, as compared to CVD copper. Because the copper seed layer may form up to 20% of the cross-sectional area of an interconnect line, this seed layer seriously hampers the electromigration characteristic of copper interconnection. Whereas the electromigration resistance of copper is high enough to sustain the wear-out in normally designed conductor lines, defect-induced electromigration failures have been observed in the PVD seed layer/electroplated copper conductor lines. Because of the high conductivity of copper, line defects such as conductor line width or thickness, when thinned down to a couple of hundred angstroms, are able to pass undetected through the electrical screen tests. Understandably, current density in these regions is considerably high during actual use, thereby causing early field fails due to electromigration.
Co-deposition of various elements with copper for high temperature application or for improving the mechanical strength is taught by Thomas in U.S. Pat. No. 5,414,301; by Shapiro et al. in U.S. Pat. No. 4,007,039; Akutsu et al. in U.S. Pat. No. 4,872,048; and, by Woodford and Bricknell in U.S. Pat. No. 4,406,858. However, when copper is co-deposited with another element, the electrical resistivity usually increases, which defies the very purpose of using copper in high performance systems.
Yet another reliability concern in copper metallurgy is corrosion. This is described below with the help of illustrations in FIGS. 1 and 1a. FIG. 1 is part of a structure of the above described interconnect scheme of the prior art, showing two levels of metal interconnections, each level defined by a double damascene method. FIG. 1a is an enlarged view of cross-section of an interconnect; wherein, copper interconnect line 9 on one level is shown making contact to lower level metal interconnect line 102 through via-stud 11. It should be understood that in a double damascene method the via stud 11 and the conductor line 102 are an integral part of one another. The copper interconnect comprises an adhesive layer 5, an optional barrier layer 6; a PVD copper seed layer 8; bulk copper layer 9 and 11, and an inorganic insulator 4 atop polyimide insulator 3.
It has been found that corrosion of copper lines generally takes place in association with the use of polyimide for interlevel insulation. This is because whenever polyimide is used for interlevel insulation its application usually involves addition of a thin layer of inorganic insulator 4. This thin layer of inorganic insulator is added either to act as an etch stop, as taught in U.S. Pat. No. 4,789,648 to Chow et al., or to reduce polyimide debris formation during chemical-mechanical polishing, as taught by Joshi et al. in U.S. Pat. No. 5,403,779 (both patents assigned to the instant assignee). The deleterious effect of this inorganic insulator layer 4 is that it prevents escape of the residual moisture in the polyimide film. Consequently, vapor pressure builds up in polyimide film, which finds a path to the copper. As a result, copper oxides and hydroxides are formed. With time and temperature, these oxides and hydroxides ultimately result in formation of voids 13 (FIG. 1) in the copper conductor. These corrosion induced voids 13 are believed to initiate from the top surface of the copper conductor for two reasons. One, liner layers 5 and 6 cover the bottom and sides of the conductor lines, but not the top surface. Second, junctions between the inorganic insulator layer 4 and the liner 5 and 6 on the conductor line side walls become disjointed during process temperature excursions, thereby providing a path for moisture to come in contact with copper. Joshi et al. U.S. Pat. No. 5,426,330, assigned to the instant assignee, teaches a method of providing a tungsten cap atop the copper conductor to prevent copper corrosion. As discussed earlier, this capping method forms undesirable metal debris during polishing, causing metal line abrasion.
Thus, despite repeated efforts, and various schemes in the prior art, manufacturing problems due to defect sensitive electromigration failure and corrosion remain. Better methods for making copper integrated circuit pattern with improved reliability and reduced defect sensitivity need to be developed.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method for fabricating high performance interconnection circuitry of sub-half-micron dimension with improved process yield and reliability.
Another object of the present invention is to provide a high conductivity copper based metallurgy with low dielectric constant polyimide passivation.
It is yet another object of the present invention to reduce defect sensitivity of copper interconnect metallurgy by improving its electromigration resistance.
It is still another objective of the present invention to provide electroplated copper interconnection lines with reduced PVD copper seed layer thickness to improve the electromigration resistance of the interconnect line.
It is a further object of the present invention to provide a method of metal capping copper lines which does not affect the metal line integrity.
The above and other objects, which will be apparent to those skilled in the art, are achieved in the. present invention which relates to a method of providing in substrates sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method may include a double damascene method using electroplated copper, where the seed layer is converted to an intermetallic layer. A layer of a copper intermetallic such as hafnium, lanthanum, zirconium, tin and titanium is provided to improve the electromigration resistance and to reduce defect sensitivity. A method is also provided to form a cap which fully covers the surface on top of copper lines formed in the substrate to improve corrosion resistance. Structure and methods are also described to improve the electromigration and corrosion resistance by incorporating carbon atoms in copper interstitial positions.
In one aspect, the present invention comprises a method for forming multilevel interconnections of copper lines isolated from one another by dielectric insulation for making contacts to electrical features in a substrate. The method comprises the steps of first preparing a substrate having a dielectric insulation layer to receive copper lines in a defined pattern and optionally depositing a metallic liner in the pattern. Subsequently there is deposited in the pattern a layer of an element capable of forming an intermetallic compound with copper and one or more layers of copper. The substrate is then heated to react the intermetallic forming element with the copper layer to form a layer of intermetallic compound in the copper layer. The intermetallic forming element is preferably selected from the group consisting of hafnium, lanthanum, titanium, tin and zirconium. The intermetallic forming element layer may be deposited before the copper layer or a copper layer is deposited before the intermetallic forming element layer. Also, the intermetallic forming element layer may be deposited before the copper layer, and a further intermetallic forming element layer may be deposited after the copper layer.
The metallic liner, the layer of intermetallic forming element and the layer of copper may be deposited by common or separate deposition techniques selected from the group consisting of sputtering, evaporation and CVD. Preferably, the metallic liner, the layer of intermetallic forming element and the layer of copper are in-situ deposited by sputtering in a single pump down, wherein the sputtering may be reactive sputtering, collimated sputtering, magnetron sputtering, low pressure sputtering, ECR sputtering, ionized beam sputtering and any combination thereof.
In a more preferred method, the present invention relates to a method of forming reliable multilevel interconnections of copper lines, at sub-micron pitch and isolated from one another by low dielectric insulation to make contacts to electrical features in a substrate. The method comprises the steps of initially depositing a pair of insulation layers on a substrate having an electrical feature, photolithographically defining a via-studs pattern on at least one of the insulation layers, partially etching the pair of insulation layers, photolithographically defining an interconnection line pattern on at least one of the insulation layers, and etching the insulation layers until the electrical feature is exposed; thereby, forming trenches and holes in the pair of insulators. Subsequently, there is deposited a liner metallurgy in the trenches and holes. A layer of an element capable of forming an intermetallic compound with copper is deposited, as well as one or more layers of copper to fill the holes and trenches. The copper is polished to remove excess metal outside of the trenches and the substrate is heated to react the intermetallic forming element with copper to form a layer of an intermetallic compound with copper.
One of the copper layers may be deposited by reactive sputtering of copper with a carbonaceous gas to incorporate carbon atoms within the lattice of deposited copper. Preferably, the thickness of the intermetallic forming element is between about 100 angstroms and 600 angstroms. The intermetallic layer may be formed beneath copper in the holes and trenches, within copper in the holes and trenches, or above copper in the holes and trenches.
In a related aspect, the present invention provides a substrate having interconnections of copper lines comprising a pair of insulation layers disposed on a substrate having an electrical feature, the insulation layers having etched via-stud patterns and etched interconnection line patterns forming holes and trenches in the pair of insulators. A metallic layer lines the trenches and holes, and copper fills the holes and trenches, with a portion of the copper including therein a region of a copper intermetallic compound.
In another aspect, the present invention relates to a method of providing copper interconnections having improved electromigration and corrosion resistance on a substrate having trenches comprising the steps of heating the substrate in a vacuum tool, introducing a carbonaceous material, in gaseous form, into the vacuum, and depositing copper metal in the substrate trenches while simultaneously incorporating interstitial atoms into the copper lattice to form copper lines in the trenches. Preferably, the substrate is held at a temperature between 100-400xc2x0 C. during the deposition and the carbonaceous material is a hydrocarbon having the formula Cx Hy or Cx Hx and containing no oxygen, nitrogen or sulphur.
In a related aspect, the invention provides a substrate having interconnections of copper lines comprising a pair of insulation layers disposed on a substrate having an electrical feature, the insulation layers having etched via-stud patterns and etched interconnection line patterns forming holes and trenches in the pair of insulators, a metallic layer lining the trenches and holes, and copper filling the holes and trenches, the copper containing from about 0.1 to 15 ppm carbon.
In a further aspect, the invention relates to a method of providing a protective cap on a substrate interconnection having a surface planar with surrounding insulation. The method comprises the steps of providing a substrate having an insulative layer thereon, etched via-stud patterns and etched interconnection line patterns forming holes and trenches within the insulative layer, and copper metallurgy filling the holes and trenches to an upper surface of the insulative layer to form a substrate interconnection. Then the copper is polished to recess its surface below the surrounding insulative layer surface. There is subsequently deposited a layer of a material for a cap over the recessed copper to a level above the surrounding insulative layer surface. The substrate is then polished to remove the cap material from regions outside of the substrate interconnection and form a cap surface planar with the surrounding insulative layer surface. Preferably, the recess thickness is about 100 angstroms to 400 angstroms, and the material for the cap is selectively deposited and chosen from the group consisting of tungsten, tungsten-silicon, tungsten-nitrogen, hafnium, zirconium, tantalum, tantalum-nitride, titanium, tin, lanthanum, germanium, carbon, chromium, chromium-chromium oxide, tin, platinum, and, combinations thereof.